In order to minimize process variation in wireless terminals, schemes for biasing power amplifiers (PAs) are migrating from voltage mode operation to current mode operation. Concurrently, advances in battery technology for wireless terminals are progressively reducing the minimum battery voltage needed to supply an operational current. In order to properly utilize the operational current for a wireless terminal supplied by a battery, a current steering digital-to-analog converter (DAC) is used to adjust the value of an output source current.
FIG. 1 is a circuit schematic depicting a related art current steering DAC 10. A first field effect transistor (FET) MP1 is coupled between a battery input VBAT and a current reference 12 that provides a reference current IREF. The current reference 12 is a bandgap type reference that derives the reference current IREF from a bandgap voltage VBG and an external resistance REXT. The reference current IREF is mirrored through a second FET MP2 that has a drain through which an output current IMP2 contributes to a DAC output current IDAC. A plurality of current mirror branches 14 each have a current mirror FET that is in series with a logic switched FET that when switched on allows a mirror copy of the reference IREF to contribute to the DAC output current IDAC. A FET MP3, a FET MP4, a FET MP5, and a FET MP6 make up the current mirror FETs for the current mirror branches 14. A FET MP7, a FET MP8, a FET MP9 and a FET MP10 make up the logic switched FETs of the current mirror branches 14.
A first current mirror branch made up of the FET MP3 and the FET MP7 selectively outputs a current IMP3 based upon a logic state of a control input B1. A low logic state for the control input B1 turns on the FET MP7 and allows the output current IMP3 to contribute to the DAC output current IDAC. A high logic state for the control input B1 turns off the FET MP7 to shut off the output current IMP3.
A second current mirror branch made up of the FET MP4 and the FET MP8 selectively outputs a current IMP4 based upon a logic state of a control input B2. A low logic state for the control input B2 turns on the FET MP8 and allows the output current IMP4 to contribute to the DAC output current IDAC. A high logic state for the control input B2 turns off the FET MP8 to shut off the output current IMP4.
A third current mirror branch made up of the FET MP5 and the FET MP9 selectively outputs a current IMP5 based upon a logic state of a control input B3. A low logic state for the control input B3 turns on the FET MP9 and allows the output current IMP5 to contribute to the DAC output current IDAC. A high logic state for the control input B3 turns off the FET MP9 to shut off the output current IMP5.
A fourth current mirror branch made up of the FET MP6 and the FET MP10 selectively outputs a current IMP6 based upon a logic state of a control input B4. A low logic state for the control input B4 turns on the FET MP10 and allows the output current IMP6 to contribute to the DAC output current IDAC. A high logic state for the control input B4 turns off the FET MP10 to shut off the output current IMP6.
There are at least two significant disadvantages attributable to the current steering DAC 10. One significant disadvantage is that each of the current mirror legs 14 needs to be cascoded to reduce variations in the DAC output current over a range of battery voltage VBAT for a given output voltage VIDAC. However, if each of the current mirror legs 14 is cascoded, a die size for the current steering DAC 10 will significantly increase. Minimization of die size is highly desirable. Therefore, any significant increase in die size is problematic.
A second disadvantage is that for proper operation of the current steering DAC 10, a voltage drop across the FETs MP2 through MP6 should be at least equal to a maximum drain-to-source voltage VDSAT. Thus, for proper operation, the current steering DAC 10 is governed by the following mathematical relationships:VIDAC>VBAT−VDSAT (non-cascoded current mirror branches)VIDAC>VBAT−2VDSAT (cascoded current mirror branches)
The output voltage VIDAC can be increased by decreasing the maximum drain-to-source voltage VDSAT, which can be accomplished by increasing the width of each of the FETs MP2 through MP6. However, in order to increase the maximum drain-to-source voltage VDSAT by a factor of two, the width of each of the FETs MP2 through MP6 must be increased by a factor of four. This is because the maximum drain-to-source voltage VDSAT is a square root function of width for a FET.
As a result of the above disadvantages, there is a need for a current DAC that does not require cascoded current mirror branches. Moreover, there is a need for a current DAC that has an increased maximum drain-to-source voltage VDSAT without needing an increase in width for each of the current mirror FETs making up the current DAC.